Semiconductor structures comprising integrated circuits made of III-V materials, in particular Field Effect Transistor (FETs) and in particular High Electron Mobility Transistors (HEMTs) have desirable electronic properties. Because bulk III-V materials can be difficult to manufacture or handle, it is known to grow layers of III-V materials on a growth substrate, and to manufacture the desired semiconductor structures on the grown layers of III-V materials. For example, it is known to grow a GaN layer on a Si growth substrate to avoid having to use a bulk GaN substrate.
However, lattice mismatches between the III-V material and the material of a growth substrate eventually create detrimental defects in the layers of III-V material grown on a growth substrate. For example, there exists a lattice mismatch between GaN and Si. It follows that a GaN layer grown on Si comprises structural defects, the number and size of which increase with the thickness of GaN grown on the Si substrate.
Because it is difficult to grow GaN on Si, for example due to the mobility of the epitaxially deposited atoms on the Si surface, it is known to first deposit a GaN buffer layer at a comparatively low temperature on the Si layer. The “low” temperature allows reducing the atom mobility and thus allow homogeneously covering the Si substrate. A main GaN layer, thereafter used for manufacturing integrated circuits such as GaN HEMTs, is then grown on top of the Gan buffer layer.
FIG. 1 shows a semiconductor structure 10 comprising a main/channel GaN layer 12 grown on top of a GaN buffer layer 14, itself grown on a Si substrate 16. A thin AlGaN barrier layer 18 was deposited on top of the main GaN layer 12.
FIG. 2 shows a GaN HEMT FET 19 formed on the structure 10. A thin gate insulator layer 20 was formed in a portion of the AlGaN barrier layer 18 and a gate electrode layer 22 was formed on top of the gate insulator layer. Source and drain electrode layers 24, 26 were formed though the AlGaN barrier layer 18 in contact with portions of the main/channel GaN layer 12, each on a side of the gate electrode layer 22. A gate field plate layer 28 was formed on top of gate electrode layer 22. A dielectric layer 30 covers HEMT 19. A source pad layer 31 was formed on top of dielectric layer 30 and connected to source electrode layer 24 by a via. A gate pad layer 32 was formed on top of dielectric layer 30 and connected to gate field plate layer 28 by a via. A drain pad layer 33 was formed on top of dielectric layer 30 and connected to drain electrode layer 26 by a via.
To achieve for example a 600V breakdown voltage for a GaN HEMT such as HEMT 19, the thickness of the GaN buffer layer 14 must be of at least 4 μm. However, forming a GaN buffer layer 14 having such a thickness on a Si substrate 16 creates physical defects in the GaN buffer layer 14, which in turn create physical defects in the GaN main/channel layer 12, which detrimentally affect the performance of any integrated circuit formed in the GaN main layer. Thus, forming on a Si substrate a GaN buffer layer 14 having the thickness required to achieve desired electrical properties can lead to poor manufacturing yields and increased manufacturing costs.
Chyurlia, P. N., Semond, F., Lester, T., Bardwell, J. A., Rolfe, S., Tang, H., & Tarr, N. G. (2010), in “Monolithic integration of AlGaN/GaN HFET with MOS on silicon<111> substrates”, Electronics letters, 46(3), disclose AlGaN/GaN HFETs and silicon MOSFETs integrated monolithically on a silicon (111) substrate. A differential heteroepitaxy technique is used to grow AlGaN/GaN HFET layers on silicon (111) substrates while leaving protected areas of atomically smooth silicon in which MOSFETs are built.
Dargis, R., Clark, A., Arkun, E., Roucka, R., Williams, D., Smith, R., & Lebby, M. (2012), in “Epitaxial Si and Gd2O3 Heterostructures: Distributed Bragg Reflectors with Stress Management Function for GaN on Si Light Emitting Devices”, ECS Journal of Solid State Science and Technology, 1(5), P 246-P 249 disclose that tensile stress in GaN layers grown directly on Si is a serious obstacle for the implementation of this technology for electronic and photonic devices. They teach that the problem can be solved by stress engineering using epitaxial buffer layers grown on a Si-substrate. Heteroepitaxial Si and Gd2O3 multilayer structures that can be used both as a tensile strain compensating buffer for GaN epitaxial layers and an efficient reflector for light emitting devices are demonstrated in this work. A three-period distributed Bragg reflector has been fabricated. It exhibits 82% reflectivity at the design wavelength of 450 nm. In situ curvature measurements of the 200 mm diameter wafers with the grown structure reveal compressive stress in the Gd2O3—Si multilayer structure. The compressive stress compensates the tensile stress which arises during subsequent growth and cooling of the GaN layer.
Lee, H. S., Ryu, K., Sun, M., & Palacios, T. (2012), in “Wafer-Level Heterogeneous Integration of GaN HEMTs and Si (100) MOSFETs”, Electron Device Letters, IEEE, 33(2), 200-202, disclose a technology for the heterogeneous integration of GaN and Si devices, which is scalable at least up to 4-in wafers and compatible with conventional Si fabrication. The key step in the proposed technology is the fabrication of a Si (100)-GaN—Si hybrid wafer by bonding a silicon (100) on insulator (SOI) wafer to the nitride surface of an AlGaN/GaN on Si (111) wafer. A thin layer of silicon oxide is used to enhance the bonding between the SOI and the AlGaN/GaN wafers. Using this technology, Si pMOSFETs and GaN high-electron-mobility transistors have been fabricated on a 4-in hybrid wafer. Due to the high-temperature stability of GaN as well as the high-quality semiconductor material resulting from the transfer method, these devices exhibit excellent performance. A hybrid power amplifier has been fabricated as a circuit demonstrator, which shows the potential to integrate GaN and Si devices on the same chip to enable new performance in high-efficiency power amplifiers, mixed signal circuits, and digital electronics.
Published Patent Application US2011-140172 discloses group III-nitride devices that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.
There exists a need for a III-V FET that can be manufactured with higher yields and lower manufacturing costs than the known III-V FETs.